Оптимизация AC/DC data acquisition: преодоление ADC challenges с continuous-time sigma-delta технологией

Сэмплирующие явления в analog-to-digital converters (ADCs) индуцируют проблемы aliasing и capacitive kickback, и для их решения дизайнеры используют фильтры и driving amplifiers, которые вводят свои собственные вызовы. Это делает достижение precision dc и ac performance в medium bandwidth application areas вызовом, и дизайнеры заканчивают trading off system goals для этого.

Статья описывает continuous-time sigma-delta (∑-Δ) ADCs, которые inherently и dramatically решают sampling проблемы, simplifying signal chains. Они убирают потребность в antialiasing filters и buffers, и решают signal chain offset errors и drift issues ассоциированные с additional components. Эти benefits shrink solution size, ease solution design и improve phase matching и overall latency системы. Статья также проводит сравнение с discrete-time converters и подсвечивает system benefits, а также constraints использования continuous-time sigma-delta ADCs.

Sampling Fundamentals

Дигитизация данных включает два фундаментальных процесса: sampling и quantization, как показано на рис. 1. Sampling — первый шаг, где continuous-time varying analog signal x(t) конвертируется в discrete-time signal x(n) используя sampling frequency fS. Результат evenly separated по периоду 1/TS (fS = 1/TS).

Второй шаг — quantization, который approximates значение этих discrete-time samples к одному из finite possible values и represented в digital code, как показано на рис. 1. Эта quantization к finite set of values приводит к error в digitization called quantization noise.

Sampling процесс также результатирует в aliasing, в котором мы видим foldback от input signals и их гармоник вокруг sample and hold clock frequency. Nyquist criterion требует, чтобы sampling frequency была at least twice highest frequency contained в signal. Если sampling frequency less than twice maximum analog signal frequency, phenomenon known as aliasing will occur.

Чтобы понять implications aliasing в обоих time и frequency domain, сначала consider case time domain representation single tone sine wave sampled как показано на рис. 2. В этом примере sampling frequency fS не at least 2fa, а only slightly more than analog input frequency fa, thus failing to meet Nyquist criterion. Notice that pattern actual samples produces aliased sine wave at lower frequency equal to fS – fa.

Corresponding frequency domain representation этого сценария показана на рис. 3.

Nyquist bandwidth defined to be frequency spectrum from dc to fS/2. Frequency spectrum divided into infinite number of Nyquist zones, each having width equal to 0.5fS. In practice, ideal sampler replaced by ADC followed by FFT processor. FFT processor only provides output from dc to fS/2; that is, signals or aliases that appear in first Nyquist zone.

Consider case single frequency sine wave of frequency fa sampled at frequency fS by ideal impulse sampler (see Figure 1). Also assume fS > 2fa. Frequency domain output of sampler shows aliases, or images, of original signal around every multiple of fS; that is, at frequencies equal to | ± KfS ± fa|, K = 1, 2, 3, 4, and so on.

Now consider case signal that is outside of first Nyquist zone in Figure 3. Signal frequency only slightly less than sampling frequency, corresponding to condition shown in time domain representation in Figure 2. Notice that even though signal is outside first Nyquist zone, its image (or alias), fS – fa, falls inside. Returning to Figure 3, it is clear that if unwanted signal appears at any of image frequencies of fa, it will also occur at fa, thereby producing spurious frequency component in first Nyquist zone.

Combating Challenges for Precision Performance

Для high performance applications, system designers need to combat quantization noise, aliasing, и switched capacitor input sampling issues resulting from sampling process. Both types precision ADCs — successive approximation registers (SARs) и sigma-delta ADCs, available in industry — designed using switched capacitor-based sampling techniques.

Quantization Noise

В идеальном Nyquist ADC, LSB size ADC will determine quantization noise that gets added to input, while doing analog-to-digital conversion. This quantization noise spread over bandwidth of fS/2. To combat quantization noise, first technique is oversampling — sampling input signal at much higher rate than Nyquist frequency to increase signal-to-noise ratio (SNR) и resolution (ENOB). In oversampling, sampling frequency chosen to be N times Nyquist frequency (2 × fIN), and as result same quantization noise has to now spread over N times Nyquist frequency. This also relaxes requirements on antialiasing filter. Oversampling ratio (OSR) defined as fS/2fIN, where fIN is signal BW of interest. As general guideline, oversampling ADC by factor of four provides one additional bit of resolution, or 6 dB increase in dynamic range. Increasing oversampling ratio results in overall reduced noise and dynamic range (DR) improvement due to oversampling is ΔDR = 10log10 OSR in dB.

Oversampling inherently used и implemented together with integrated digital filter и decimation functionality. Basic oversampling modulator in sigma-delta ADC shapes quantization noise such that most of it occurs outside bandwidth of interest, resulting in increased overall dynamic range at low frequencies, as shown in Figure 4. Digital low-pass filter (LPF) then removes quantization noise outside bandwidth of interest, and decimator reduces output data rate back to Nyquist rate.

Noise shaping — other technique to reduce quantization noise. In sigma-delta ADCs, low resolution quantizer (one bit to five bits) used inside loop after loop filter. DAC used as feedback to subtract quantized signal from input, as shown in Figure 5.

Integrator will keep summing up quantization error resulting in shaping of quantization noise to higher frequencies, which then can be filtered using digital filter. Figure 6 illustrates power spectral density (PSD) of output x[n] of typical sigma-delta ADC. Noise-shaping slope depends on order of loop filter H(z) (see Figure 11) and is (20 × n) dB/decade, where n is order of loop filter. Sigma-delta ADC achieves high resolution in-band by combination of noise shaping and oversampling. In-band bandwidth equal to fODR/2 (ODR stands for output data rate). Higher resolution can be obtained by increasing order of loop filter or by increasing oversampling ratio.

Aliasing

To combat aliasing в high performance applications, higher order antialiasing filters used to avoid any amount of foldback. Antialiasing filter is low-pass filter that band limits input signal и ensures that there is no frequency component in signal beyond bandwidth of interest that can fold back. Filter performance will depend on how close out-of-band signal is to fS/2, and amount of attenuation required.

Для SAR ADCs, gap между input signal BW и sampling frequency not huge, hence we need higher order filter that calls for complex, higher order filter design with more power and more distortion. For example, if 200 kSPS sampling speed SAR has input BW of 100 kHz, antialiasing filter will need to reject input signal >100 kHz to make sure there is no aliasing. This requires very high order filter. Figure 7 shows steep curve demand.

If sampling speed of 400 kSPS chosen to relax order of filter, rejection needed for >300 kHz input frequency. Increasing sampling speed will increase power, and for double speed, power would also be doubled. Further oversampling at cost of power will further relax antialiasing filter requirement, as sampling frequency much higher than input BW.

In sigma-delta ADCs, input oversampled at much higher OSR, so antialiasing filter requirement relaxed as sampling frequency much higher than input BW, as shown in Figure 8.

Figure 9 gives idea of AAF complexity для SAR и discrete-time sigma-delta (DTSD) architectures. If we take -3 dB input bandwidth of 100 kHz to achieve 102 dB attenuation at sampling frequency fS, second-order antialiasing filter will be needed for DTSD ADC while getting same attenuation at fS will require fifth-order filter using SAR ADC.

For continuous-time sigma-delta (CTSD) ADC, attenuation inherent, so we don't need any antialiasing filter.

These filters can be pain point для system designers, и they have to optimize them for droop they provide in band of interest and provide as much rejection as possible. They also add a lot of other errors like offset, gain, phase error, and noise to system, thus reducing its performance.

Also, high performance ADCs are differential in nature, so we need twice the number of passive components. To get better phase matching в multichannel applications, all components in signal chain must match well. As result, components with tighter tolerance are required.

Switched Capacitor Input

Switched capacitor input sampling relies on settling time of sampled input onto capacitor, creating demand for charging/discharging transient current when sampling switch turned on/off. This is called kickback on input и calls for input driving amplifier that can support these transient currents. Also, input required to be settled at end of sampling time and accuracy of input sampled determines performance of ADC, implying that driving amplifier needs to settle quickly after kickback event. This leads to need for high bandwidth driver that can support fast settling и absorb kickback of switched capacitor operation. In switched capacitor inputs, whenever sampling is ON, driver immediately has to supply charge for hold capacitor. This sudden surge in current can only be provided in time if driver has sufficient bandwidth capabilities. Due to parasitics of switch, there will be kickback on driver at time of sampling. If kickback does not settle before next sampling, it will result in error being sampled, thus corrupting ADC input.

Figure 10 shows kickback on DTSD ADC. If, for example, sampling frequency is 24 MHz, data signal needs to settle within 41 ns. Since reference is also switched capacitor input, high bandwidth buffer also needed on reference input pin. These input signal and reference buffers add to noise and drop overall performance of signal chain. Furthermore, distortion components from input signal driver (around S&H frequency) further adds to antialiasing requirements. Also, with switched capacitor inputs, changes in sampling speed will result in varying input current. This could result in retuning of system for reducing gain error generated in driver or preceding stage while driving ADC.

Continuous-Time Sigma-Delta ADC

CTSD ADC is alternative sigma-delta ADC architecture that takes advantage of principles such as oversampling и noise shaping, but that has alternative means of implementing sampling operation that delivers significant system benefits.

Figure 11 shows comparison of DTSD architecture и CTSD architecture. As we see in DTSD architecture, input is sampled before the loop. Loop filter H(z) is discrete in time и implemented using switched capacitor integrators. Feedback DAC is also switched capacitor-based. As there is sampling at input, which will result in aliasing problem from f_S, additional antialiasing filter required on input before it is sampled.

CTSD does not have sampler at input. Rather, it is sampled at quantizer inside the loop. Loop filter is now continuous-time using continuous-time integrators, and so is feedback DAC. Similar to quantization that gets shaped, aliasing due to sampling gets shaped as well. This results in almost non-sampling ADC, making a class of its own.

Sampling frequency of CTSD is fixed, unlike in DTSD where sampling frequency of modulator can be easily scaled. Also, CTSD ADCs are known to be less tolerant to jitter than switched capacitor equivalents. Off-the-shelf crystal or CMOS oscillators provide low jitter clocks to ADCs locally, which helps avoid transmitting low jitter clock over isolation и reduces EMC.

The two primary benefits of CTSD are inherent alias rejection и resistive inputs for signals and reference.

Inherent Antialiasing

Moving quantizer inside the loop results in inherent alias rejection. As shown in Figure 12, input signal passes through loop filter before being sampled and foldback (alias) error, which is introduced at quantizer, also sees this filter. Signal and alias error will see same noise transfer function as sigma-delta loop, and both will have similar noise shaping as quantization noise in sigma-delta architectures. Thus, frequency response of CTSD loop naturally rejects input signals around integer multiples of sampling frequency, acting as antialiasing filter.

Resistive Input

Having resistive inputs on signal and reference inputs makes it easier to drive than sample-and-hold configurations. With constant resistive inputs, there is no kickback and the driver can be completely removed. The input is distortion free, as shown in Figure 13. And since input resistance is constant, retuning of system for gain errors is also eliminated.

Analog inputs can be bipolar even though ADC has unipolar supply. This can remove need for level shifting from bipolar front end to ADC. The dc performance of ADC may not be the same as input resistor now has input common-mode dependent current as well as input current.

The reference load is also resistive, which reduces switching kickback, hence a separate reference buffer is not required. The resistor for a low-pass filter can be made on-chip so that it can track along with on-chip resistive load (as they could be of same material), for reduced gain error temperature drift.

CTSD architecture is not new, but megatrends in industrial и instrumentation markets demand dc и ac precision performance at higher bandwidths. Moreover, customers prefer a single platform design that would cater to most of their solutions in order to reduce their time to market.

CTSD architecture has been the choice in a broad set of applications ranging from high performance audio to cellular handset RF front end due to a number of advantages over other types of ADCs. The benefits include greater amenability to integration и low power consumption, but also, and possibly more importantly, because using a CTSD solves a number of significant system-level problems. Due to a number of technological shortcomings, the use of CTSD has previously been limited to relative audio frequency/bandwidth и lower dynamic range. Therefore, high performance Nyquist rate converters such as successive approximation ADCs и oversampled DTSD converters have been the mainstream solution for precision, high performance/medium bandwidth applications.

However, recent technology breakthroughs have enabled overcoming many limitations. For example, the AD7134 from Analog Devices supports high precision dc to 400 kHz bandwidth ADC based on CTSD that achieves substantially higher performance specifications, while providing dc accuracy and, in turn, enabling the solution for a number of important system-level problems in high performance instrumentation applications. The AD7134 also integrates an asynchronous sample rate converter (ASRC) providing data at variable data rates derived from the fixed sampling speed of CTSD. The output data rate can be independent of modulator sampling frequency and can enable successful use of CTSD ADCs for different granular throughputs. The flexibility to change the output data rate at a granular level also enables users to use coherent sampling.

Inherent alias rejection removes the need for an antialiasing filter, which results in fewer components and a smaller solution size. More importantly, performance issues that come along with an antialiasing filter such as droop, errors such as offset, gain, and phase error, and noise in the system are no longer present. An antialiasing filter also adds significantly to the overall latency in the signal chain depending upon the rejection needed. Removal of the filter removes this delay completely, enabling precision conversion in noisy digital control loop applications.

With no antialiasing filter at the system level, phase matching in multichannel systems can be vastly improved. This is especially useful in applications demanding low channel-to-channel mismatch such as vibration monitoring, power measurements, data acquisition modules, and sonar. Because of their inherent filtering action, CTSD ADCs are also immune to any kind of interference at the system level, as well from within the IC itself. In DTSD ADCs and SAR ADCs, care has to be taken such that there is less interference when the ADC is sampling. Also, there would be immunity from interference on power supply lines due to the inherent filtering action. With constant resistive analog inputs and reference inputs, the driver requirement can be completely removed as well. Again, this addresses performance concerns such as errors like offset, gain, phase error, and noise to the system are no longer there.

The struggle to achieve the precision performance is very minimal as the number of designed elements is significantly reduced. This result in faster design time, faster time to market for customers, easier BOM management, and reliability. Removal of an antialiasing filter, a driver, and a reference buffer will significantly reduce the system board area. An instrumentation amplifier can be used to directly drive the ADC. For example, with the AD7134, as it is a differential input only ADC, a differential in-amp such as the LTC6373 can be used as a driver. The comparison in Figure 14 shows the signal chain for a discrete-time-based signal chain and a continuous-time-based signal chain. Our experiment shows 70% of area savings when compared to an equivalent discrete-time-based signal chain, making it an excellent choice for high density multichannel applications.

In conclusion, this approach offers significant system size reduction, simplifies the signal chain design, makes the system more robust, and reduces the overall time to market with easy design-in without trading any performance parameters demanded by precision instrumentation applications.

References

1. Kester, Walt. "MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design." Analog Devices, Inc., 2009.
2. Pavan, Shanti. "Alias Rejection of Continuous-Time Δ∑ Modulators with Switched Capacitor Feedback DACs." IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 58, No. 2, February 2011.
3. Schreier, Richard and Gabor C. Temes. Understanding Delta-Sigma Data Converters. John Wiley and Sons, 2005.

Acknowledgements

The author would like to thank Abhilasha Kawle, Avinash Gutta, and Roberto Maurino for their support on this article.