Детектор последовательности на Verilog: построение надёжного КА для распознавания образов

Частый пример конечного автомата (КА) — детектор последовательности, где аппаратный дизайн должен обнаружить фиксированный образец в потоке битов на входе.

Пример

Детектор последовательности 1011:

module det_1011 ( input clk, input rstn, input in, output out );
parameter IDLE = 0, S1 = 1, S10 = 2, S101 = 3, S1011 = 4;
reg [2:0] cur_state, next_state;
assign out = cur_state == S1011 ? 1 : 0;
always @ (posedge clk) begin
    if (!rstn) cur_state <= IDLE;
    else cur_state <= next_state;
end
always @ (cur_state or in) begin
    case (cur_state)
        IDLE  : begin if (in) next_state = S1; else next_state = IDLE; end
        S1    : begin if (in) next_state = IDLE; else next_state = S10; end
        S10   : begin if (in) next_state = S101; else next_state = IDLE; end
        S101  : begin if (in) next_state = S1011; else next_state = IDLE; end
        S1011 : begin next_state = IDLE; end
    endcase
end
endmodule

Тестбенч

module tb; reg clk, in, rstn; wire out; reg [1:0] l_dly; reg tb_in; integer loop = 1;
always #10 clk = ~clk;
det_1011 u0 ( .clk(clk), .rstn(rstn), .in(in), .out(out) );
initial begin
    clk <= 0; rstn <= 0; in <= 0; repeat (5) @ (posedge clk); rstn <= 1;
    // Направленный паттерн
    @(posedge clk) in <= 1; @(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1;
    // Паттерн завершён
    @(posedge clk) in <= 0; @(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1;
    @(posedge clk) in <= 0; @(posedge clk) in <= 1; @(posedge clk) in <= 1; // Паттерн снова
    // Случайный стимул
    for (int i = 0 ; i < loop; i ++) begin l_dly = $random; repeat (l_dly) @ (posedge clk); tb_in = $random; in <= tb_in; end
    #100 $finish;
end endmodule

Simulation Log показывает выход out = 1 в моменты обнаружения паттерна 1011.

В дизайне есть ошибка. Можете её найти?